1. Technical Field
This invention relates to integrated circuit devices and a process of making the same, and in particular, this invention relates to microcavity structures which utilize a pinning layer to pin the microcavity structures in selected areas, applications thereof and process of making the same. This invention also relates to the specially shaped contact vias created with the process and the integrated circuit therewith.
2. Related Art
As integrated circuit devices become smaller, spacing between electronic components and conductors becomes ever more critical. Such components and/or conductors are typically separated and isolated by a dielectric material. A vacuum has the best relative dielectric constant (1.0). The dielectric constant of air is just slightly higher than that of a vacuum.
Doped glass is commonly used as an integrated circuit dielectric because its melting point can be made significantly lower than that of regular glass or of other dielectric materials. Boro-Phosphorus Silicate Glass (BPSG) is one exemplary type of doped glass. After deposition over a pattern of polysilicon conductors, for example, a BPSG dielectric layer can be put through a high temperature reflow process, usually at about 900xc2x0 C., which reflows the BPSG, smooths its surface, and eliminates xe2x80x98as depositedxe2x80x99 voids between the polysilicon conductors for facilitating subsequent processing steps.
A typical BPSG material, however, has a significantly higher relative dielectric constant, e.g., about 3.6 to 4.6. One technique which has been used to reduce the relative dielectric constant of BPSG glass is to allow cavities to form in the material at appropriate locations. The cavities can form during the chemical vapor deposition (CVD) process in spaces between raised features, such as conductors or semiconductor mesas. These cavities are essentially air or vacuum filled and therefore constitute a low dielectric constant region between the raised features. In this manner, for example, capacitive coupling between adjacent conductors can be reduced, thereby enhancing device signal speed.
Despite speed improvements, which voids in BPSG films can provide, their proper size and shape formation is presently difficult to control. For example, voids between adjacent conductors are formed when a BPSG layer is deposited on top of a polysilicon conductive pattern. However, during the reflow process, the voids may disappear if the spaces between polysilicon conductors are large enough or the deposited film is thin enough. The voids formed when a BPSG layer of about 7000 Angstroms is deposited over a circuit topography of conductors separated by about 1.0 micron are typically eliminated during reflow. Unfortunately, it is not possible to forgo the reflow process without also losing the smoothness and related benefits such a structure can provide in subsequent processing.
Thus, as with the above-discussed example, there is a need for an improved method for controllably fabricating cavities for semiconductor and micro-machine applications, such as for pressure sensing, chromatography, fabrication of capacitive components, and selectively isolating components and conductors, etc. Further, there is a need for a method to create self-aligned contact vias which do not short circuit to neighboring conductors. Further there is a need to be able to shape contact vias.
Microcavity structures or voids are controlled for providing structures, such as self-aligned contact vias, by pinning a microcavity in selected areas using a pinning layer which is then selectively removed. A structure such as the contact via is formed in a method which steps include: providing a layer having a pair of raised features; depositing a void forming material over said layer; depositing a pinning material over said void forming material, wherein the pinning material acts to pin a void in said void forming material; and annealing the materials.
Another method of this invention includes the steps of: providing a substrate with topography; depositing a void forming material over said substrate to thereby form voids; depositing a pinning material over said void forming material wherein the pinning material pins the void forming material; patterning said pinning material to remove the pinning material from areas where void formation is not desired; and annealing the voids in areas where the pinning material remains to seal the void forming material in areas where the second material has been selectively removed.
The contact via and method for making the same saves both time and expense over existing methods. For example, it does not require the use of pressurizing the microcavities to prevent collapse of the microcavity structures. Another advantage is more accurate control of size, shape and location of void formation. Numerous other advantages and features of the method will become readily apparent from the following detailed description of the preferred embodiment, the accompanying drawings and the appended claims.
In another embodiment in accordance with the present invention is provided an integrated circuit device comprising a contact via having a non-cylindrical bottom portion. The integrated circuit device may have either a frustoconical or arrowhead shaped bottom portion.
In a further embodiment, a contact via having non-parallel side walls is provided.
In yet another embodiment in accordance with the present invention is provided a contact via for use in a semiconductor device, the contact via having non-parallel side walls. The contact via may also have either a frustoconical or arrowhead shaped bottom portion.
The above devices allow for contact vias with non-cylindrical shape.